module down_link_top(
		//input
		clk_1m,
		clk_250k,
		rst_n,
		up_link_req,
		async_rxd,
		sram_ack,
		sram_busy,
		sram_data_out,//data read from sram ctrl
		test_mode,
        
		//output 
		down_link_req,
		down_sram_wr,
		down_sram_rd,
		down_sram_addr,
		down_sram_data,//data write to the sram
		sram_mux,
		rxd_fliter,
		oe_8ch,
		end_flag,
        ch_125k_en,
        data,
        data_val
);
parameter N = 8;
input clk_1m,
	  clk_250k,
	  rst_n,
	  up_link_req;
input [7:0] async_rxd;
input sram_ack,
	  sram_busy;
input [7:0] sram_data_out;
input test_mode;

output down_link_req,
	   down_sram_wr,
	   down_sram_rd;
output [12:0] down_sram_addr;
output [7:0]  down_sram_data;
output sram_mux;
output [7:0] rxd_fliter;
output [7:0] oe_8ch;
output [7:0] end_flag;
output [1:0] ch_125k_en;
output [7:0] data,
             data_val;
             
 
wire check_over;
wire [7:0]oe_8ch;
wire [7:0]jud_err;
wire [7:0]end_flag;
wire down_sram_wr,
	 down_sram_rd;
wire [12:0] down_sram_addr;
wire [7:0]  down_sram_data;

wire [12:0] sram_addr_ch8;
wire [12:0] sram_addr_down;
wire        wr_sram_req;
wire        init_resp_req;
wire        time_out;
wire        oe_timer;
wire        time_20ms;

assign 	 down_sram_addr = 	(wr_sram_req  || init_resp_req)  ?  sram_addr_down : sram_addr_ch8;
	 
timer timer_ins(
		//input
		.clk_1m(clk_1m),
		.rst_n(rst_n),
		.oe(oe_timer),
		//output
		.check_over(check_over),
		.time_out(time_out),
        .time_20ms(time_20ms)
);

down_link_ctrl   down_link_ctrl_ins(
		//input
		.clk_1m(clk_1m),
		.rst_n(rst_n),
		.jud_err(jud_err),
		.end_flag(end_flag),
		.time_out(time_out),
		.up_link_req(up_link_req),
		.sram_ack(sram_ack),
        .test_mode(test_mode),
        .time_20ms(time_20ms),
		//output
		.oe_8ch(oe_8ch),
		.down_link_req(down_link_req),
		.down_sram_wr(down_sram_wr),
		.down_sram_addr(sram_addr_down),
		.down_sram_data(down_sram_data),
		.wr_sram_req(wr_sram_req),
		.init_resp_req(init_resp_req),
		.sram_mux(sram_mux),
        .ch_125k_en(ch_125k_en),
        .oe_timer(oe_timer)
);


dut_8channel dut_8ch_ins (
		//input
		.async_rxd(async_rxd),   //signal from dut
		.check_over(check_over),  //signal from dut
		.clk_1m(clk_1m),		 //signal from dut
		.clk_250k(clk_250k),
		.oe_8ch(oe_8ch),			 //signal from dut
		.rst_n(rst_n),		 //signal from dut
		.sram_ack(sram_ack), //arbitrator  sram_ack signal
		.sram_busy(sram_busy),//arbitrator sram_busy signal
		.sram_data_out(sram_data_out),// data from scram ctrl 
	
		//output
		.jud_err(jud_err),   //dut jud_err
		.end_flag(end_flag),   //dut end_flag
		.sram_addr(sram_addr_ch8),  //arbitrator 
		.sram_rd(down_sram_rd),	//arbitrator
		.rxd_fliter(rxd_fliter),
		.oe_128(oe_128),
        .data(data),
        .data_val(data_val)
);


endmodule 